Fetch-Decode-Execute (FDE) Cycle

Overview

The Fetch-Decode-Execute (FDE) Cycle is a fundamental process that the CPU uses to execute instructions. This cycle repeats for each instruction in a program, enabling the CPU to process tasks sequentially and efficiently. Understanding the stages of the FDE cycle is essential as it provides insight into how the CPU processes instructions, manipulates data and interacts with memory.

Key Components of the FDE Cycle

The FDE cycle consists of three main stages, each involving specific CPU components, especially the registers. Here's a breakdown of each stage, including how data and addresses are transmitted and the role of registers in each phase.

Fetch Stage

Purpose

The fetch stage retrieves the next instruction to be executed from memory.

Process

1. Program Counter (PC): Holds the address of the next instruction in memory.

• The address stored in the PC is transferred to the Memory Address Register (MAR).

2. Memory Address Register (MAR): Temporarily holds the address of the instruction.

• The address bus transmits this address from the MAR to the main memory.

3. Memory Data Register (MDR): Once the instruction is located, it is sent from memory to the MDR.

• The data bus transfers the instruction from the main memory to the MDR.

4. Current Instruction Register (CIR): The MDR then passes the instruction to the CIR, where it is held for decoding.
5. Program Counter (PC) Increment: The PC increments to the next memory address, preparing for the next cycle.

Effect on Registers

• PC is updated to point to the next instruction.
• MAR holds the address of the instruction being fetched.
• MDR temporarily holds the fetched instruction before transferring it to the CIR.
• CIR stores the fetched instructions for use in the next stage.

Decode Stage

Purpose

In the decode stage, the CPU interprets the fetched instruction to determine the actions required for execution.

Process

1. Control Unit (CU): The CU reads the instruction in the CIR and decodes it.

• The CU translates the instruction into a series of signals that prepare the CPU for execution.

2. Identify Required Components: The CU identifies any data, registers, or ALU operations needed for execution.

Effect on Registers

• CIR: Holds the instruction throughout the decode process.
• Control Unit: Decodes the instruction, often referencing other registers (e.g., the Accumulator (ACC) if an arithmetic operation is required).

Execute Stage

Purpose

The execute stage performs the actions specified by the decoded instruction.

Process

1. Arithmetic and Logic Unit (ALU): If the instruction is arithmetic or logical, it is executed here.

• The ALU may perform operations (like addition or comparison) on data held in registers (often the ACC).

2. Data Transfer: If the instruction requires data to be moved, it may involve:

• Registers: Data may move from the ACC to another register.
• Memory: Data may be written to or read from memory, using the MAR and MDR.

3. Updating the Program Counter: After executing, the PC is already set to the next instruction, allowing the cycle to repeat.

Effect on Registers

• ACC: Holds the result of the ALU operation, if applicable.
• MDR and MAR: Used if additional memory operations are needed during execution.
• PC: Already prepared to fetch the next instruction by the end of this stage.

Summary of Register Usage in Each Stage

Stage	Registers Involved	Purpose
Fetch	PC, MAR, MDR, CIR	Retrieve the next instruction from memory.
Decode	CIR, Control Unit	Interpret the instruction in the CIR.
Execute	ALU, ACC, MAR, MDR	Perform the operation or data transfer.

Data and Address Transmission

• Address Bus: Transmits memory addresses from the MAR to main memory.
• Data Bus: Transfers data between memory and the CPU, particularly to and from the MDR.
• Control Bus: Carries control signals from the Control Unit to coordinate data flow and execution timing.

Note Summary