5.1 Explain polarisation when used in the operation of a liquid crystal display (LCD) - NSC Electrical Technology Digital - Question 5 - 2024 - Paper 1

In a common anode seven-segment display, all anodes of the LEDs are connected to a positive voltage, while the individual cathodes connect to ground to light the segments. Conversely, in a common cathode display, all cathodes are connected to ground, and the anodes of each segment are connected to a positive voltage to illuminate the segments. This distinction affects how the segments are activated in circuit designs.

To complete the diagram of the three-bit parallel adder, include three Full Adders (FA). Label the inputs as B0, B1, B2, A0, A1, A2, and carry inputs as Cin for the first adder. The sum outputs from each adder become the final outputs S0, S1, and S2, with the carry out from each adder leading into the next.

Upon pressing switch 7, the output binary code corresponds to the active high signals generated from the inputs. Identify which switches are activated and the resulting binary code based on their positions.

Pulse triggering refers to the ability of a flip-flop to change its output state with each clock pulse during its active high period. This means that the flip-flop can toggle its state when an input signal meets the defined conditions, allowing for stable and predictable transitions.

In constructing the full adder using two half adders, connect the first half adder to inputs A and B, producing a sum (S1) and carry (C1). The second half adder takes S1 and Cin as inputs, producing the final sum (Sum) and an additional carry (C2). Feed C1 and C2 into an OR gate to provide the final carry output (Cout).

To complete the JK Flip-Flop circuit, connect J and K inputs through AND gates controlled by the clock signal. The output of these AND gates will feed into the SR Latch configuration, ensuring proper toggling behavior as specified.

The output waveform for Q will change based on the clock pulses. Since Q starts LOW, observe changes when J and K are HIGH or LOW synchronously with the clock. Each clock pulse will determine state changes, where Q toggles between HIGH and LOW according to J and K inputs.

The circuit in FIGURE 5.8 is asynchronous, as the outputs are not governed by a unified clock signal but rather respond to the individual flip-flop conditions based on the input clock pulses.

A disadvantage of up/down counters is that they tend to operate slower than standard up or down counters, primarily due to the complexity of the logic needed to manage the bidirectional counting mechanism.

In the four-bit serial-in: parallel-out shift register design, use four D flip-flops connected sequentially. Each flip-flop's output serves as an input to the next, with the serial input feeding into the first flip-flop. The clear signal allows for setting all outputs to zero, while multiplexing ensures all parallel outputs are accessible.