4.1 Name TWO methods to display information in digital systems - NSC Electrical Technology Digital - Question 4 - 2021 - Paper 1

In a common anode configuration, the anodes of all LEDs in the seven-segment display are connected to the positive voltage supply. Each segment is activated by applying a low voltage (ground) to the corresponding cathode terminal. This allows individual segments to light up while sharing a common power source.

Transistor coupling in LED seven-segment displays is employed to control the current flowing through the segments. In the circuit shown in FIGURE 4.3, a transistor acts as a switch, allowing or blocking current to the LED segment based on the control signal. This ensures efficient operation and protects the components from excess current.

Polarisation of light refers to the orientation of light waves in particular directions. In an LCD, light travels through polarising filters, which allow only specific orientations of light to pass through. When light transitions through the liquid crystals, its polarisation can change based on the applied electric field, enabling control over the display's visibility and contrast.

The circuit depicted in FIGURE 4.5 is a decoder. It converts binary inputs into a distinct output line corresponding to the input combination.

The logic circuit of a full adder can be drawn as follows:

• Inputs: A, B, Cin (carry-in).
• Outputs: Sum, Cout (carry-out).
• Create two XOR gates for the sum:
  • First XOR gate takes inputs A and B.
  • Second XOR gate takes the output of the first XOR and Cin for the final sum.
• For Cout:
  • Use two AND gates: one for A and B, and another for A and Cin.
  • Combine the outputs of both AND gates using an OR gate.

The output waveforms diagram would show the states of Q and Q' corresponding to the inputs of S and R. Depending on the clock pulse, the outputs will change states according to the flip-flop rules.

The three-bit parallel adder circuit comprises three full adder circuits connected in a row. Each adder processes one bit from the two three-bit numbers. Carry outputs from each full adder connect to the next higher significant bit, ensuring accurate summation of the bits along with any carry.

1. Synchronous Counter: Counts in sync with a clock signal, ensuring that all bits change state simultaneously.
2. Asynchronous Counter: Count changes occur asynchronously, with the flip-flops triggered by the previous flip-flop's output rather than a common clock.

Combinational logic circuits use logic gates (AND, OR, NOT) as their basic elements and produce outputs solely based on current inputs.
Sequential logic circuits, however, include memory elements (like flip-flops) along with logic gates, meaning their outputs depend not only on the present inputs but also on past inputs, providing a notion of state.

The counter depicted in FIGURE 4.12 is a three-bit synchronous down counter.

1. Parallel-in: Serial-out (PISO) Shift Register: Data is loaded in parallel and shifted out serially.
2. Serial-in: Parallel-out (SIPO) Shift Register: Data is loaded serially and read out in parallel.

A = Serial data
B = Clock

In a serial-in: serial-out shift register, data bits are loaded sequentially into the register from the input (A) on each clock pulse (B). The data moves from one flip-flop to the next, shifting until it reaches the output. Each bit is retained in its flip-flop until shifted out.