4.1 Name TWO methods to connect the LEDs of an LED seven-segment display to the supply - NSC Electrical Technology Digital - Question 4 - 2020 - Paper 1

The circuit in FIGURE 4.2 is identified as a sourcing digital output circuit, where the transistor (T1) acts as a switch to control the LED load. When the input is active, T1 allows current to flow from the supply through the LED, illuminating it.

The two classes of synchronous flip-flops are:

1. Pulse triggered (master/slave): These flip-flops change state on the leading or trailing edge of a clock pulse.
2. Edge triggered: These flip-flops change state only at specific moments on the clock edge, either rising or falling.

In a complete 4-bit parallel adder, there should be four Full Adders (F/A) connected in series. The carry-out (C_out) of each Full Adder is connected to the carry-in (C_in) of the next higher bit's Full Adder.

The truth table of the binary-to-decimal decoder for inputs A and B is as follows:

The function of a decoder is to convert binary inputs into a specific output line. It takes a binary code and activates the corresponding output which represents a recognizable decimal form, either as a digit or a character.

The two group classifications of logic circuits are:

1. Combinational logic circuits: These circuits have outputs that depend only on the current inputs.
2. Sequential logic circuits: These circuits have outputs that depend on both current inputs and past states (memory elements).

The truth table for the RS latch is:

The output waveforms of the RS latch would show Q changing based on the inputs S and R. When S is high and R is low, Q goes high. When S is low and R is high, Q goes low. If both S and R are high simultaneously, it is an invalid state.

Propagation delay refers to the time taken for the change in input to affect the output in each flip-flop of an asynchronous ripple counter. Each flip-flop introduces a certain delay, and this delay cascades through the counter, leading to a total propagation delay equal to the sum of the individual flip-flop delays.

The output waveforms will show changes at the output Q of the counter based on the input clock pulses. Output A, B, and C will represent the counts. The waveforms should update sequentially with each clock pulse.

The AND gate in FIGURE 4.11 ensures that FF2 does not produce an incorrect reading on the second clock pulse. It requires both inputs Q0 and Q1 to be high at the fourth clock pulse, allowing the next state transition to occur correctly.

The register in FIGURE 4.12 is identified as a 4-bit parallel-in-parallel-out register.

A is labeled as the 4-bit data input and B is labeled as the 4-bit data output.

This register allows for parallel loading of data. When the clock signal is activated, data present at the data input pins is captured and stored in the register. The stored data can then be outputted simultaneously from the output pins when needed.